The PCI Express 5.0 spec will bring 128 gigabytes per second to your PC, someday Credit: AMD YouTubeSupplied Art
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The PCI Express 5.0 spec will bring 128 gigabytes per second to your PC, someday

The PCIe 5 spec promises up to 128 gigabytes per second (GBps) of throughput via a x16 configuration—enabling faster storage, graphics, and other components for future PCs. But while the PCIe 5 spec was announced Wednesday by the PCI SIG trade group, that’s just a step toward actual implementation of the interface. PCIe 3 is the active standard, and PCIe 4 is just coming out.

At Computex in Taipei earlier this week, AMD touted the combination of the Ryzen 7 3800X CPU and its X570 motherboard as the first PCI Express 4.0-ready PC. Between the X570 and the Ryzen platform, up to 40 lanes of PCIe 4.0 are available, AMD said. 

PCIe 5's arrival date in actual PC hardware is anyone's guess. In a statement issued through the PCI SIG’s official blog, AMD said that it would support PCIe 5.0, but not when. “We expect to bring our first PCIe 4.0 specification CPUs to market this year and look forward to meeting the future bandwidth demands of end-users with PCIe 5.0 technology,” said Gerry Talbot, an AMD fellow in the company’s Technology and Engineering Group.

AMD chief executive Lisa Su was equally noncommittal when asked about PCIe 5.0 in a group Q&A interview during Computex. “Well, I think it remains to be seen, things always seem like they’re going to be faster,” Su said. “And things always take a little bit longer than you expect.”

Meanwhile, Intel has yet to announce support for PCIe 4.0, let alone PCIe 5, though the company issued a statement as part of the PCI SIG blog post . Flagship chipsets like Intel’s X299 support up to 44 PCI Express 3.0 lanes. “As a founding promoter of PCI Express architecture, we fully support the newly-released PCIe 5.0 specification, and look forward to continuing the PCI Express specification tradition of high-performance, multi-platform, open interconnect,” Debendra Das Sharma, an Intel fellow and director of I/O technology and standards, said as part of the PCIe blog post. 


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